Experiment-NOT, OR, & NOT GATES
Experiment No.-1
Aim: Synthesis and simulation of NOT, OR, NOR GATE.
Apparatus Used:-
| S.No | Items | Specification | Quantity |
| 1 | Computer set | P-4, 2GB DDR | 01 |
| 2 | Software (Tool) | Xilinx 10.1 | 01 |
Theory:-
NOT Gate:
The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way.
OR Gate:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation.
NOR Gate:
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high.The symbol is an OR gate with a small circle on the output. The small circle represents inversion.
NOT Gate implementation:
library ieee;
use ieee.std_logic_1164.all;
entity NOTGATE is
port( A: in std_logic;
C: out std_logic);
end NOTGATE;
architecture func of NOTGATE is
begin
C <= NOT A;
end func;
OR Gate implementation: library ieee;
use ieee.std_logic_1164.all;
entity orGate is
port( A, B : in std_logic;
F : out std_logic);
end orGate;
architecture func of orGate is
begin
F <= A or B;
end func;
NOR Gate implementation:-library ieee;
use ieee.std_logic_1164.all;
entity norGate is
port( A, B : in std_logic;
F : out std_logic);
end norGate;
architecture func of norGate is
begin
F <= A nor B;
end func;
Observation/ Analysis
RTL schematic of NOT Gate
RTL schematic of OR Gate
RTL schematic of NOR Gate
Results:
NOT GATE SIMULATION
OR GATE SIMULATION
NOR GATE SIMULATION
